Semiconductor processing methods of forming contact openings, methods of forming memory circuitry, methods of forming electrical connections, and methods of forming dynamic random access memory (DRAM) circuitry

ABSTRACT

Methods of forming contact openings, memory circuitry, and dynamic random access memory (DRAM) circuitry are described. In one implementation, an array of word lines and bit lines are formed over a substrate surface and separated by an intervening insulative layer. Conductive portions of the bit lines are outwardly exposed and a layer of material is formed over the substrate and the exposed conductive portions of the bit lines. Selected portions of the layer of material are removed along with portions of the intervening layer sufficient to (a) expose selected areas of the substrate surface and to (b) re-expose conductive portions of the bit lines. Conductive material is subsequently formed to electrically connect exposed substrate areas with associated conductive portions of individual bit lines.

TECHNICAL FIELD

[0001] This invention relates to semiconductor processing methods offorming contact openings, methods of forming memory circuitry, methodsof forming electrical connections, and methods of forming dynamic randomaccess memory (DRAM) circuitry.

BACKGROUND OF THE INVENTION

[0002] Semiconductor processing typically involves a number ofprocessing steps including material deposition, masking with maskinglayers, and etching to define integrated circuitry structures. At eachprocessing step there are risks that the integrated circuitry beingformed can be compromised. As the complexity of integrated circuitryincreases, so too can the processing complexities and the risk that theformed circuitry will be compromised. One of the factors thatcontributes to the risk of compromised integrated circuitry is thenumber of masking steps that are used in a particular processing flow.The more masking steps, the more the likelihood is that a misalignmentcan occur. Another problem which has implications insofar as deviceintegrity is concerned relates to conductive material undesirablyremaining behind over wafer areas. Such remnant material is sometimesreferred to as “stringers” and can cause device components to short toone another. Accordingly, there is a need within the industry to reducethe likelihood that these and other problems will affect the integratedcircuitry being formed.

[0003] This invention arose out of concerns associated with improvingthe methods by which integrated circuitry is formed and reducing therisks that the formed circuitry will be compromised.

SUMMARY OF THE INVENTION

[0004] Methods of forming contact openings, memory circuitry, anddynamic random access memory (DRAM) circuitry are described. In oneimplementation, an array of word lines and bit lines are formed over asubstrate surface and separated by an intervening insulative layer.Conductive portions of the bit lines are outwardly exposed and a layerof material is formed over the substrate and the exposed conductiveportions of the bit lines. Selected portions of the layer of materialare removed along with portions of the intervening layer sufficient to(a) expose selected areas of the substrate surface and to (b) re-exposeconductive portions of the bit lines. Conductive material issubsequently formed to electrically connect exposed substrate areas withassociated conductive portions of individual bit lines.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0006]FIG. 1 is a diagrammatic sectional view of a wafer fragment inprocess, and an exemplary conductive line formed thereover.

[0007]FIG. 2 is a diagrammatic sectional view of a plurality ofconductive lines.

[0008]FIG. 3 is a view of the FIG. 2 conductive lines at a differentprocessing step.

[0009]FIG. 4 is a view of the FIG. 3 conductive lines at a differentprocessing step.

[0010]FIG. 5 is a top plan view of a semiconductor wafer fragment.

[0011]FIG. 6 is a view of the FIG. 5 wafer fragment at a differentprocessing step.

[0012]FIG. 7 is a view of the FIG. 6 wafer fragment at a differentprocessing step.

[0013]FIG. 8 is a diagrammatic sectional view of the FIG. 7 waferfragment taken along line 8-8 in FIG. 7.

[0014]FIG. 9 is a diagrammatic side sectional view which is taken alongline 9-9 in FIG. 7.

[0015]FIG. 10 is a view of the FIG. 7 wafer fragment at a differentprocessing step.

[0016]FIG. 11 is a view of the FIG. 9 wafer fragment at a differentprocessing step.

[0017]FIG. 12 is a view of the FIG. 11 wafer fragment at a differentprocessing step.

[0018]FIG. 13 is a view of the FIG. 10 wafer fragment at a differentprocessing step.

[0019]FIG. 14 is a view of the FIG. 12 wafer fragment at a differentprocessing step.

[0020]FIG. 15 is a view of the FIG. 14 wafer fragment at a differentprocessing step.

[0021]FIG. 16 is a view of the FIG. 15 wafer fragment at a differentprocessing step.

[0022]FIG. 17 is a view of the FIG. 13 wafer fragment at a differentprocessing step.

[0023]FIG. 18 is a view which is taken along line 18-18 in FIG. 17 andillustrates a portion of conductive material which supports capacitorstructure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0025] Referring to FIG. 1, a semiconductor wafer fragment is indicatedgenerally at 20 and comprises a semiconductive substrate 22. In thecontext of this document, the term “semiconductive substrate” is definedto mean any construction comprising semiconductive material, including,but not limited to, bulk semiconductive materials such as asemiconductive wafer (either alone or in assemblies comprising othermaterials thereon), and semiconductive material layers (either alone orin assemblies comprising other materials). The term “substrate” refersto any supporting structure, including, but not limited to, thesemiconductive substrates described above.

[0026] An exemplary conductive line or gate is shown generally at 100.The illustrated conductive line and the description of the formation ofthe various NMOS FETs and PMOS FETs which follow constitute but one wayof forming specific conductive lines. Accordingly, other conductivelines and methods of forming the same can be utilized in the context ofthe invention. Various aspects of the invention are described in thecontext of memory circuitry, and in particular, dynamic random accessmemory (DRAM) circuitry. Such circuitry is typically formed over a waferand can be categorized as including array circuitry (i.e. circuitryformed within a memory array) and peripheral circuitry (i.e. circuitryformed outside the memory array and operably coupled therewith).Conductive lines, such as line 100, can be formed to constitute botharray circuitry and peripheral circuitry. An exemplary conductive lineconstruction can comprise a conventional gate stack, e.g., a gate oxidelayer 102, a polysilicon layer 104, and a tungsten silicide layer 106. Adielectric cap 108 can be provided over the conductive material and canbe formed from suitable materials such as oxides, nitrides, and thelike. Following a patterning and etching step in which the conductivelines are formed, a lightly doped drain (LDD) diffusion step can takeplace to form lightly doped drain regions (not specifically shown).Subsequently, a layer 110 comprising an oxide material formed throughdecomposition of tetraethylorthosilicate (TEOS) can be deposited to athickness of around 600 Angstroms.

[0027] Referring to FIG. 2, three illustrative conductive lines areshown generally at 112, 114, and 116. Line 112 comprises an NMOS FET,line 114 comprises a PMOS FET, and line 116 comprises a conductive linewhich is formed within the memory array. An exemplary processingtechnique for forming NMOS FETs includes forming photoresist over thesubstrate and exposing conductive lines which are to constitute thegates of NMOS FETs. Accordingly lines 114 and 116 would be covered withphotoresist. Layer 110 is subsequently etched to form sidewall spacers118, 120. Source/drain implants are then formed (not shown), i.e. byimplanting arsenic or boron. Subsequently, the resist is stripped,followed by formation of an oxide layer 122 from decomposition of TEOSto a thickness of around 100-200 Angstroms. Such layer can be formedover all of the lines.

[0028] Referring to FIG. 3, PMOS FETs can be formed by depositing alayer 124 of polysilicon (or nitride) to a thickness of around 500Angstroms, forming photoresist (not shown) over conductive lines 112 and116, and etching layers 124, 122, and 110 over line 114 to form sidewallspacers 126, 128. Source/drain regions can be formed throughimplantation of BF₂ followed by an angled implantation of phosphorous.Subsequently, the photoresist can be stripped.

[0029] Referring to FIG. 4, material of layers 124 and 122 can besubsequently removed from over lines 112, 116, followed by deposition ofa layer 130 comprising oxide formed through decomposition of TEOS, to athickness of about 300 Angstroms. The above description constitutes butone method for forming spacers associated with the conductive lines.

[0030] The discussion now proceeds with reference to FIG. 5 whereinsubstrate 22 is shown prior to formation of the above describedconductive lines. A plurality of isolation regions 24 are provided andbetween which are defined a plurality of active areas 26. Isolationregions 24 can be formed through known shallow trench isolation (STI) orother techniques.

[0031] Referring to FIG. 6, a plurality of conductive lines 28 areformed over substrate 22 and preferably comprise a series of word linesfor a memory array, such as a dynamic random access memory (DRAM) array.The illustrated conductive lines 28 can correspond to conductive line116 described above, in connection with FIGS. 1-4.

[0032] Referring to FIGS. 7 and 8, a first insulative oxide layer 30(FIG. 8) is formed over substrate 22 and word lines 28. An exemplary andpreferred material for layer 30 comprises borophosphosilicate glasswhich can be deposited to a thickness of between about 10,000 to 14,000Angstroms. Layer 30 can be subsequently reflowed and chemical mechanicalpolished to planarize the layer. The planarization of layer 30preferably terminates over conductive lines 28.

[0033] A plurality of bit lines 32 are formed over planarized firstinsulative layer 30. Exemplary bit lines 32 can comprise a layer ofpolysilicon or a conductive barrier layer 34, a silicide or refractivemetal (e.g., W) layer 36, and a dielectric cap 38 formed from suitabledielectric materials (including WN_(x), TiN_(x), etc.) such as oxides,nitrides, and/or both. Such layers are subsequently patterned into theindividual bit lines shown in FIG. 7. Sidewall spacers are preferablyprovided over the bit lines and can comprise an oxide formed throughdecomposition of TEOS, or a suitable nitride deposited throughlow-pressure chemical vapor deposition.

[0034] Collectively, bit lines 32 and word lines 28 comprise a matrix(FIG. 7) which is formed over the substrate. In a preferred embodiment,the matrix defines a memory array comprising a dynamic random accessmemory (DRAM) array. Insulative oxide layer 30 (FIG. 8) defines anintervening layer which separates the word lines and bit lines. Forpurposes of the ongoing discussion, word lines 28 define a first seriesof conductive lines, and bit lines 32 define a second series ofconductive lines which are disposed over the first series of conductivelines. Within the array are defined a plurality of substrate contactareas, i.e. source/drain diffusion regions, with which electricalcommunication is desired. In a preferred embodiment, substrate contactareas 33 a (FIG. 7) comprise bit line contact areas and substrate areas33 b comprise capacitor contact areas.

[0035] Referring to FIGS. 9 and 10, a masking layer 40 is formed oversubstrate 22 and patterned to define a plurality of openings 42 over,and expose portions of bit lines 32, which in this example, constitutethe uppermost conductive lines of the first and second series ofconductive lines. The openings also define an area over the bit linecontact areas 33 a.

[0036] Referring to FIG. 11, unmasked insulative material of theindividual bit lines is removed to expose underlying conductive material36, 34. The insulative material is preferably etched, selectively,relative to intervening insulative oxide layer 30. Such constitutesexemplary partially forming of a first contact opening which exposesconductive material of the individual bit lines over insulative layer30. The removing of the bit line material can remove some of material30. In one aspect, an angled etch can be conducted to expose onlysidewall portions of the individual bit lines. In a preferred aspect, ananti-reflective coating layer (not shown) can be deposited and overwhich the illustrated masking layer 40 is formed. A reactive ion etch(RIE) can be conducted which is highly selective to the underlyinginsulative oxide layer 30. Such etch exposes the illustrated top portionof bit lines 32, as well as sidewall portions thereof which includesconductive material of both layers 34, 36. After the exposing of theconductive portions of the bit lines, the photoresist is stripped away.

[0037] Referring to FIG. 12, a layer of material 44 is formed oversubstrate 22 and the exposed conductive portions of the individual bitlines. Such material at least partially fills the contact opening formedthrough the removal of the insulative portions of the bit linesmentioned above. Preferably, layer 44 is a second insulative oxide layercomprising borophosphosilicate glass. Layer 44 can be formed to athickness of 8,000 to 10,000 Angstroms, and thereafter reflowed andplanarized, as by chemical mechanical polishing which terminates on orover individual bit lines 32.

[0038] Referring to FIG. 13, a patterned masking layer 46 is formed oversubstrate 22 and defines a plurality of openings 48 over the substratenode locations with which electrical communication is desired. In theillustrated example, such substrate node locations include both the bitline contact areas 33 a and the capacitor contact areas 33 b.

[0039] Referring to FIGS. 14 and 15, material from over substrate 22 isremoved through masked openings 48 sufficiently to form second contactopenings which expose both the conductive material of the individual bitlines which was previously exposed, and the individual substrate nodelocations with which electrical communication with the bit lines isdesired. The removal of such material also exposes node locations 33 b(FIG. 13) over which capacitors are to be formed. The first and secondinsulative oxide layers 30 and 44 can be selectively etched relative tomaterial from which the bit lines and word lines are formed. Such etchforms contact openings which are self-aligned relative to both the wordlines and the bit lines and defines bit line contact openings andcapacitor contact openings. Exemplary etch chemistries can include gasessuch as CF₄, CHF₃, CH₂F₂, Ar, and O₂. Reactor power can be provided ataround 700 Watts, with pressures around 30 mTorr. Other exemplaryprocessing can take place as described in U.S. Pat. No. 5,286,344, whichis incorporated by reference herein.

[0040] Referring to FIG. 15, conductive material 50 is formed over thesubstrate and within the bit line contact openings and the capacitorcontact openings. Accordingly, material 50 establishes electricalcommunication or electrically connects individual bit line contact areas33 a with their associated individual bit lines. Such conductivematerial also provides material over the capacitor contact areas whichwill ultimately form conductive plugs therewithin. An exemplary andpreferred material is polysilicon which can be deposited andsubsequently isolated within the individual openings as by reactive ionetch or other suitable isolation techniques. Such constitutes forming aplurality of conductive interconnects which establish electricalcommunication between the bit lines and the substrate node locations.

[0041] Referring to FIG. 16, insulative material 52 is formed oversubstrate 22 and conductive material 50. In the illustrated example,insulative material 52 comprises a first layer 54 and a second layer 56.Materials can be selected for layers 54, 56 which are selectivelyetchable relative to one another. As an example, layer 54 can comprisean oxide formed through decomposition of TEOS deposited to a thicknessof 400 Angstroms, and layer 56 can comprise a nitride layer formed to athickness of 500 Angstroms. Alternatively, layer 54 can comprise anitride layer formed to a thickness of 400 Angstroms, and layer 56 cancomprise an oxide layer formed through decomposition of TEOS to athickness of 800 Angstroms.

[0042] Referring to FIGS. 16 and 17, a patterned masking layer 58 isformed over the substrate and preferably the conductive material whichis formed over the individual bit line contact areas 33 a.

[0043] Referring to FIGS. 17 and 18, insulative material 52 is removedfrom over capacitor contact areas 33 b. Capacitors are formed over andin electrical communication with conductive material 50 which is formedwithin the capacitor contact openings and in electrical communicationwith node locations 33 b (FIG. 17). For illustrative purposes only, thecapacitors include a storage node layer 60, a dielectric layer 62, and acell plate layer 64. Various known techniques and materials can beutilized in forming the capacitors. In some embodiments, the storagenode layer 60 is formed from polysilicon presenting a roughened surface,such as hemispherical grain polysilicon, as represented by the shadingin FIG. 18, in order to provide increased capacitance.

[0044] The above described method has advantages in that polysiliconstringers (which can cause shorting) are reduced, if not eliminated.Additionally, less masks are needed which reduces processing complexity.The method also provides for self-aligned contact openings to be etchedat the same time, with the openings being self-aligned to both the wordlines and the bit lines.

[0045] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor processing method of forming a contact openingcomprising: partially forming a first contact opening over a firstinsulative material over a node location with which electricalcommunication is desired; at least partially filling the contact openingwith a second insulative material; and etching a second contact openingthrough the second insulative material and the first insulativematerial.
 2. The semiconductor processing method of claim 1 , whereinthe etching outwardly exposes the substrate node location.
 3. Thesemiconductor processing method of claim 1 , wherein the etchingcomprises selectively etching the second contact opening relative to adifferent insulative material disposed within the confines of the secondcontact opening.
 4. The semiconductor processing method of claim 1 ,wherein the first and second insulative materials are different.
 5. Thesemiconductor processing method of claim 1 , wherein the etchingcomprises selectively etching the second contact opening relative to adifferent insulative material which is disposed over a conductivecomponent within the second contact opening, the second contact openingbeing self-aligned relative to the conductive component.
 6. Asemiconductor processing method of forming memory circuitry comprising:forming an array of word lines and bit lines over a substrate surfaceand having a intervening insulative layer therebetween; outwardlyexposing conductive portions of the bit lines; after the outwardlyexposing, forming a layer of material over the substrate and exposedconductive portions of the bit lines; removing selected portions of thelayer of material and the intervening layer sufficient to (a) exposeselected areas of the substrate surface at least some of which definingbit line contact areas with which electrical communication is desired,and (b) re-expose said conductive portions of the bit lines; and aftersaid removing, forming conductive material to electrically connectindividual bit line contact areas and associated conductive portions ofindividual bit lines.
 7. The semiconductor processing method of claim 6, wherein the outwardly exposing of the conductive portions of the bitlines comprises masking over portions of the bit lines and etchingunmasked portions of the bit lines selectively relative to theintervening insulative layer.
 8. The semiconductor processing method ofclaim 6 , wherein the forming of the array of word lines and bit linescomprises: forming a series of word lines over the substrate surface;forming an insulative oxide layer over the word lines; planarizing theinsulative oxide layer, said insulative oxide layer defining saidintervening layer; and forming a series of bit lines over theintervening insulative oxide layer.
 9. The semiconductor processingmethod of claim 6 , wherein: the forming of the array of word lines andbit lines comprises: forming a series of word lines over the substratesurface; forming an insulative oxide layer over the word lines;planarizing the insulative oxide layer, said insulative oxide layerdefining said intervening layer; and forming a series of bit lines overthe intervening insulative oxide layer; and the outwardly exposingcomprises: masking the bit lines with a masking layer having a pluralityof openings therein; etching bit line material through the openingssufficiently to expose said conductive portions.
 10. The semiconductorprocessing method of claim 6 , wherein: the forming of the array of wordlines and bit lines comprises: forming a series of word lines over thesubstrate surface; forming an insulative oxide layer over the wordlines; planarizing the insulative oxide layer, said insulative oxidelayer defining said intervening layer; and forming a series of bit linesover the intervening insulative oxide layer; the outwardly exposingcomprises: masking the bit lines with a masking layer having a pluralityof openings therein; and etching bit line material through the openingssufficiently to expose said conductive portions; and the forming of thelayer of material over the substrate comprises: forming a secondinsulative oxide layer over the substrate; and planarizing said secondinsulative oxide layer.
 11. The semiconductor processing method of claim6 , wherein the forming of the layer of material over the substratecomprises forming an insulative oxide layer over the substrate andplanarizing said insulative oxide layer.
 12. The semiconductorprocessing method of claim 6 , wherein the removing of theselected-portions of the layer of material and the intervening layercomprises: masking over the individual word lines; and etching the layerof material and the intervening layer selective to word line material.13. The semiconductor processing method of claim 6 , wherein theintervening layer separating the word lines and bit lines and the layerof material which is formed over the substrate compriseborophosphosilicate glass.
 14. The semiconductor processing method ofclaim 6 , wherein the forming of the conductive material comprises:depositing polysilicon over the bit line contact areas and theassociated conductive portion of the individual bit lines; and removingpolysilicon sufficient to isolate individual polysilicon plugs over thebit line contact areas.
 15. The semiconductor processing method of claim6 , wherein other of the selected areas, which are exposed by theremoving of the selected portions of the layer of material, definecapacitor contact areas with which electrical communication withindividual capacitors is desired.
 16. The semiconductor processingmethod of claim 15 , wherein forming of the conductive material toelectrically connect individual bit line contact areas and associatedconductive portions of individual bit lines also comprises forming saidconductive material over and in electrical communication with thecapacitor contact areas.
 17. The semiconductor processing method ofclaim 16 further comprising: forming insulative material over theconductive material electrically connecting the individual bit linecontact areas and the associated conductive portions of the individualbit lines; and forming a plurality of capacitors over the substrate,individual capacitors being in electrical communication with respectiveindividual capacitor contact areas through the conductive materialformed thereover.
 18. In a matrix of conductive lines formed over asubstrate comprising first and second- series of conductive lines, oneseries being formed over another, an electrical connection method ofestablishing electrical communication between at least some of the linesand substrate node locations comprising: forming a masking layer overthe substrate defining a plurality of openings over an uppermost of theseries of lines; removing material of individual lines of the uppermostseries of lines and exposing conductive material of the individuallines; after the removing of the material of the individual lines,forming insulative material over the substrate and the exposedconductive material; masking over the substrate and defining maskopenings over substrate node locations with which electricalcommunication is desired; removing insulative material through the maskopenings and other substrate material sufficient to expose both theconductive material of the individual lines which was previously exposedand the substrate node locations with which electrical communication isdesired; and forming a plurality of conductive interconnects over thesubstrate, the interconnects establishing electrical communicationbetween second exposed conductive material of the individual lines andindividual respective substrate node locations.
 19. The electricalconnection method of claim 18 , wherein: the removing of the insulativematerial and the other substrate material exposes other substrate nodelocations with which electrical communication is desired, the othersubstrate node locations being different from those substrate nodelocations which are in electrical communication with the second exposedconductive material through individual interconnects; and the forming ofa plurality of conductive interconnects also comprises formingconductive material over the other substrate node locations.
 20. Theelectrical connection method of claim 19 further comprising: forminginsulative material over the individual interconnects; and after theforming of the insulative material, forming a plurality of capacitorsover the substrate and in electrical communication with the conductivematerial formed over the other substrate node locations.
 21. Theelectrical connection method of claim 18 , wherein the matrix comprisesa portion of a memory array and the first and second series ofconductive lines respectively comprise word lines and bit lines of thememory array.
 22. The electrical connection method of claim 21 , whereinthe memory array comprises a DRAM array.
 23. A semiconductor processingmethod of forming DRAM circuitry comprising: forming an array of wordlines and bit lines over a substrate, the bit lines being formed overthe word lines and atop a first generally planarized insulative layerportions of which are disposed between the word lines and bit lines;forming a masking layer over the substrate having openings therein whichexpose portions of the bit lines; selectively etching bit line materialthrough the openings relative to the insulative layer sufficient toexpose conductive portions of the bit lines; forming a second insulativelayer over the substrate and the exposed conductive portions of the bitlines; etching a plurality of contact openings through the first andsecond insulative layers sufficient to expose underlying substrate areasand to reexpose the conductive portions of the bit lines within some ofthe contact openings, the contact openings defining bit line contactopenings and capacitor contact openings; and depositing conductivematerial within the contact openings and in electrical communicationwith the exposed substrate areas, some of said material establishingelectrical communication between the re-exposed conductive portions ofthe bit lines and respective associated exposed substrate areas.
 24. Thesemiconductor processing method of claim 23 , wherein etching of the bitline material comprises etching material from both the top and sides ofindividual bit lines sufficient to expose the conductive material. 25.The semiconductor processing method of claim 23 , wherein etching of thebit line material comprises conducting an angled etch sufficient toexpose conductive portions of the bit lines along individual sidewallsthereof.
 26. The semiconductor processing method of claim 23 furthercomprising: forming insulative material over conductive material withinthe bit line contact openings; and forming capacitors over and inelectrical communication with conductive material within the capacitorcontact openings.
 27. A semiconductor processing method of forming aDRAM array comprising: forming a plurality of conductive lines over asubstrate, at least some of which comprising word lines; forming a firstinsulative layer over the substrate and word lines; forming a pluralityof bit lines over the first insulative layer, the word lines and bitlines defining an array having substrate contact areas with whichelectrical communication is desired, the substrate contact areascomprising both bit line contact areas and capacitor contact areas;exposing conductive portions of the bit lines; forming a secondinsulative layer over the substrate and exposed conductive portions ofthe bit lines; exposing bit line contact areas, capacitor contact areas,and previously-exposed bit line conductive portions through at least oneof the first and second insulative layers; forming conductive materialover and in respective electrical communication with exposed bit linecontact areas and capacitor contact areas, conductive material over thebit line contact areas establishing electrical communication with thepreviously-exposed bit line conductive portions; masking over theconductive material formed over the bit line contact areas; and forminga plurality of storage capacitors over the substrate, individualcapacitors being in electrical communication with individual respectivecapacitor contact areas through the respective conductive materialformed thereover.
 28. The semiconductor processing method of claim 27 ,wherein the exposing of the conductive portions of the bit linescomprises selectively etching material of the bit lines relative to thefirst insulative material.
 29. The semiconductor processing method ofclaim 27 , wherein the exposing of the conductive portions of the bitlines comprises not exposing any word line material.
 30. Thesemiconductor processing method of claim 27 , wherein the exposing ofthe conductive portions of the bit lines comprises conducting an angledetch sufficient to expose sidewall material of the bit lines.
 31. Thesemiconductor processing method of claim 27 , wherein the exposing ofthe conductive portions of the bit lines comprises etching bit linematerial from the top and sides of the individual bit lines.
 32. Thesemiconductor processing method of claim 27 , wherein the exposing ofthe conductive portions of the bit lines comprises selectively etchingbit line material from the top and sides of the individual bit linesrelative to the first insulative material.
 33. The semiconductorprocessing method of claim 27 further comprising planarizing the secondinsulative layer prior to exposing the bit line contact areas, capacitorcontact areas, and bit line conductive portions.
 34. The semiconductorprocessing method of claim 27 , wherein the exposing of the bit linecontact areas, capacitor contact areas, and bit line conductive portionscomprises etching both the first and second insulative layersselectively relative to both bit line and word line material.